1. Field of the Invention
This invention relates to the field of field effect transistor devices, and more particularly to the production of gallium arsenide field effect transistor devices and the formation of such devices.
2. Description of the Prior Art
In producing GaAs field effect transistors, one of the most significant factors limiting the saturated output power of such devices is the drain-gate avalanche breakdown voltage. To have a sufficiently high drain-gate breakdown voltage, a minimum drain-to-gate spacing must be maintained. In an interdigitated layout, such as that utilized in achieving high power and high frequency, misalignment in the lithography process produces a distribution of drain-gate spacing. The smallest drain-gate spacing in this distribution limits the breakdown voltage of the entire field effect transistor (FET). Although it is possible to design a layout such that the minimum drain-gate spacing produced by the maximum alignment error will give adequate breakdown voltage, in such a layout the drain-source spacing, and therefore the channel resistance, can be unnecessarily large. The larger the channel resistance, the larger the knee voltage (the voltage at which the linear region and the saturation region of an FET intersect). The saturated output power of a GaAs FET is proportional to the difference between the drain-gate breakdown voltage and the knee voltage for a given drain-source saturation current. Accordingly, the power performance of a GaAs FET is compromised when a large drain-source spacing is chosen to compensate for alignment errors. Additionally, in such a layout the finger in the interdigitated layout with the smallest drain-gate spacing has the largest gate-source spacing. A large gate-source spacing translates into large source resistance, which in turn degrades the frequency response of the FET.
In a monolithic microwave integrated circuit (MMIC) where more than one FET is utilized, and where wafer yield is of ultimate importance, since few MMICs can be produced per wafer, the non-uniform and non-reproduceable frequency and power performance can cause unnecessary design iterations and unacceptable yield. Therefore, the distribution of drain-gate spacing in an MMIC has to be kept small.
Prior art attempts to produce satisfactory devices avoiding the above noted problems have not been totally satisfactory. The first of those attempts may be referred to generally as the symmetrically self-aligned gate process. This technique is commonly utilized in digital GaAs integrated circuit devices. A symmetrically selfaligned gate process is illustrated in FIGS. 1a and 1b. Referring to FIG. 1a, the process begins with a body 1 which includes a lightly doped N-type channel region 2, extending into body 1 from surface 3. On surface 3 of body 1, a refractory metal, such as TiW is applied by the process of evaporation or sputtering, and patterned by either lift-off or etching to form gate 5 at the center of region 2. Following the formation of gate 5, a photoresist 6 is applied and patterned as illustrated in FIG. 1b, forming openings 7 and 8. Following the patterning process to open areas 7 and 8, an ion implant process is performed to provide the highly doped N-type source region 9 and drain region 10 in body 1. It will be noted that the structure provides two heavily doped regions (source region 9 and drain region 10) symmetrically about gate 5, with both the source region 9 and drain region 10 being in close proximity to the sides of gate 5. This small separation between gate 5 and the heavily doped drain region 10 makes the drain-gate breakdown voltage unacceptably low for power applications.
A second prior art technique for producing a gate for an integrated circuit device is illustrated in FIGS. 2a-2c. Referring to FIG. 2a, the process begins with body 12, which may be of GaAs material, into which a lightly N doped region 13 has been formed. To provide source and drain regions, first photoresist 14 is applied to surface 15 and patterned to produce openings 16 and 17. Openings 16 and 17 are produced by using a first mask through which light is shined to activate photoresist 14, after which photoresist is removed in the exposed areas to produce the structure of FIG. 2a. Following the production of opening 16 and 17, an ion implantation step is performed to produce the highly doped N-type source region 18 and highly doped N-type drain region 19. Following the production of the source and drain regions, first photoresist 14 is removed and second photoresist 20 is applied to surface 15 and patterned as indicated in FIG. 2c to provide opening 21 for the deposition of a gate on surface 15. The patterning of the device in FIG. 2c involves the use of a second mask to expose photoresist 20 and define opening 21 through which gate material will be deposited. The introduction of a second mask to define the location of the gate leads to the difficulties of gate-to-drain region 19 being varying distances apart. As pointed out above, the gate-to-drain spacing is quite important and the utilization of a second mask to produce a device in the manner illustrated in FIGS. 2a through 2c is highly frought with difficulties since the second mask alignment is very critical.
A third category of processes utilized in the production of GaAs FET devices is referred to as the off-set self-aligned gate-source process. This process involves a slight variation on the prior art processes illustrated in FIGS. 1a and 1b, and is not totally satisfactory, as will be more fully described below, as mask alignment problems (particularly with the second mask) produces non-uniform gate-to-drain region distribution on the surface of a wafer. This technique is described in an article entitled "A Refractory Self-Aligned Gate Process for Monolithically Combined Microwave and Digital GaAs ICs", published in the IEEE Internatinal Microwave Symposium Digest, 1987 MTT-S, pp. 665-668, by A. Geissberger, R. Sadler, E. Griffin, I. Bahl, H. Singh and M. Drinkwine. The following is a simplified explanation of the off-set self-aligned gatesource process using FIGS. 3a, b and c to describe such process. The process begins, referring to FIG. 3a, with body 24, having a lightly doped N-type region 25 extending into body 24 from surface 26. On surface 26 refractory gate material is applied and patterned by a first photomask to form the gate structure 29. The next step in the process involves covering surface 26 with a photoresist 30, which as will be noted in FIG. 3b extends above the top of gate 29. Second photoresist 30 being patterned by a second mask to produce openings 31 and 32 which will provide the to-be-formed source region (below opening 31) and drain region (below opening 32). Since a second mask is required to define the location of the drain region (which will be below opening 32), this leads to the possibility of additional misalignment and across the surface of the wafer gate-to-drain opening distance will vary providing the above described undesirable varying distribution of gate-to-drain region. Following the patterning and removal of second photoresist 30 illustrated in FIG. 3b, the source and drain regions are doped, typically by ion implantation, to produce the structure illustrated in FIG. 3c having source region 33 and drain region 34. Although utilizing the processes of FIG. 3a through 3c provide an asymmetrical configuration, that is drain region 34 is further displaced from the closer edge of gate 29 than is source region 33 from the nearest edge of gate 29, as indicated above, this process requires the utilization of a second mask to produce opening 32 and the utilization of a second mask with its attendant misalignment problems can result in a non-uniform distribution of the gate-to-drain region spacings across the surface of the wafer. Accordingly, although this is an improvement, it does not totally satisfy the requirements for a process providing uniform spacing across the surface of a wafer.